Packaging and verifying the integrity of advanced and connected semiconductor devices is proving challenging when it comes to gaining user trust in new applications. This topic has become even more critical as circuit design, semiconductor manufacturing, chip design tools, and IP involves collaborating with different teams and/or parties across the globe.
ASIC packaging design is widely considered to be one of the most critical steps in semiconductor manufacturing. One factor that influences its prominence is the need to keep systems performing faster and better, despite the demise of Moore’s Law.
In recent years, the industry has turned to chiplets to integrate many chips into one package. The advantages are a more easily specialized system and improved yield, among other benefits. However, chiplets have led to a significant shift in the fabless semiconductor industry, where the targeted end product becomes a small, specialized ASIC to be combined in the same package with a general-purpose processor and other chiplets.
From design to foundry: GDSII and tape-out
GDSII data is a hierarchical database, that describes millions — or billions — of polygons in an integrated circuit (IC), with a much smaller number of database records in a file. The hierarchy is valuable and important because IC designs tend to reuse the same geometric patterns over and over again.
Calma GDSII stream format is the most popular format for interchange in the design of integrated circuits. It is the standard binary file format for transferring 2D graphical design data. It contains a hierarchy of structures, with each structure containing elements (boundary/polygon, path/polyline, text, box, structure references, and structure array references).
The small-file database is crucial because it has to be processed by the foundry after it has been taped out.
For the fabless chip designer, post-GDSII services are crucial
As mentioned earlier, chip design has become increasingly complicated as manufacturers integrate more features in the package. That’s why fabless semiconductor companies need to rely on the expertise of post-GDSII services.
For example, a smartphone CPU designed as one chip might include cache memory, a GPU to manage the display, several cores, and basic connectivity, all within one package. That level of sophistication not only makes for a very complex database, but also serves as a recipe for disaster. This is why analyzing the interaction between components, and simulating other factors such as thermal-dissipation power consumption, is of paramount importance for the product to perform correctly for several years.
This has resulted in the demand for post-GDSII backend services to increase exponentially across all high-performance–computing ASIC applications. Additionally, OEM companies face both technical challenges and engineering talent limitations associated with traditional backend services.
In addition to the above, Alchip Technologies, the high-performance–computing ASIC leader, offers several post-GDSII packaging services for high-performance chip design, including:
- Chip-on-wafer-on-substrate, a 2.5D IC through-silicon via interposer-based packaging technology. First developed by TSMC, which is expected to announce a true 2.5D INFO capability, the process also includes online debugging and active thermal control.
- A two-signoff verification option to accommodate both design economics and enhanced yield objectives. Standard signoff verification includes DRC/LVS/ERC checks that guard against fatal manufacturing errors. A second design option calls for additional focus on electrical, DFT, STA, and/or clock verification, depending on specific customer requirements.
“Given the complex demands placed on today’s high-performance–computing ASICs, it’s not surprising that there’s a keen focus on proven production, packaging, and test and assembly capabilities,” said Johnny Shen, president and CEO of AIchip Technologies. “These once-pedestrian practices are now highly prized for their capabilities to wring out every last nth of performance power and area.”
If you require ASIC packaging services, including post-GDSII verification, wafer fabrication, supply chain management, testing, logistics, and other related services, please contact your nearest AIchip office for more information.