TORONTO — The latest first-generation protocol announced by the JEDEC Solid State Technology Association has been driven by increased demand for DRAM capacity and bandwidth, as well as a flexible method for attaching emerging, persistent memory in computing systems.
The JESD304-4.01 DDR4 NVDIMM-P Bus Protocol provides a formal specification for hybrid DIMM technologies such as NVDIMM-P, which enable design engineers to combine the access speeds of DDR with the reliability and capacity of non-volatile memories to improve data management, said Jonathan Hinkle, who chairs JEDEC’s Hybrid DIMM Task Group standardizing NVDIMMs.
A key goal of the standard was to find ways to attach and leverage a variety of persistent memories such as magnetoresistive random-access memory (MRAM), Resistive random-access memory (ReRAM), and phase change memory (PCRAM), including Intel’s Optane, during runtime just like DRAM.
Hinkle said the DDR4 NVDIMM-P Bus Protocol pairs well with current efforts to build out the Compute Express Link (CXL) ecosystem, which in part is aimed at reducing how far data has to move within a system and getting it onto the most appropriate media for the workload. “The new memory types have different kind of characteristics,” he said. “We want low latency, very fast access to these new memories, but the new memories don’t necessarily play by the same rules as DRAM.”
For one thing, DRAM is deterministic — it behaves only exactly how the processor expects, said Hinkle. The various new persistent memory types take a few more nanoseconds here or there in comparison, or certain operations may need to happen to get the return of data. “We needed to build in flexibility into a new protocol.” The goal is to make sure any emerging memory can take advantage of the fast pipe available to it; the abstraction of memory media provided by the protocol enables almost any memory media on the DDR channel, including DRAM, MRAM or 3D Xpoint media such as Optane.
However, said Hinkle, a balance must be struck between abstraction and getting lower latency access — full abstraction would allow for anything to be connected but that would increase latency and reduce performance in favor of flexibility. “We try to make it so that you can get responses back very quickly from very fast memory.”
The protocol also supports expanded memory addressing as to allow for higher memory capacity, as well as plug and play interoperability through standard dual in-line memory module (DIMM) sockets and run-time interoperable with DDR DRAM DIMMs on the same bus.
The DDR4 NVDIMM-P Bus Protocol was designed to be compatible with DDR4, rather than the latest and greatest DDR5, because DDR4 is in wide production. Hinkle said the next major iteration of the protocol will include DDR5 support. This first iteration took more than three years to hash out, and the impetus was to get an open standard out to respond to an industry requirement and accommodate different suppliers offering different types of emerging, persistent memories rather than have a propriety solution take hold. Intel is shipping Optane DIMMs today that could be easily plugged in because of the DDR4 NVDIMM-P Bus Protocol, he said. “It’s really a standard way that we can touch all sorts of different types of memories has all the features that we can support like the persistence of the memory and the higher capacity.”
The concept of being able to accommodate a variety of persistent memories (also known as storage class memories) is not a new endeavour. Although the Non-Volatile Memory Express (NVMe) protocol was primarily designed with the goal of unlocking the performance of NAND flash as Solid States Drives (SSDs) previously limited by architectures for hard drives, it also has the potential of being used as an interface for other persistent memory-based devices such MRAM and Optane media, not just flash-based SSDs.
The more recent and rapid development of CXL is also about flexibility when it comes to memory options, volatile or non-volatile. It comprises three protocols, each of which can be used alone or in combination for specific use cases, including accelerators in memory to support dense computation or memory buffers to support memory capacity expansion and storage class memory.
Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.
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